To reduce power consumption and enhance the performance per area, some integrated circuits, e.g., central processing unit (CPU), graphics processing unit (GPU), system on chip (SOC) have reduced the core operating voltage, while the surrounding chips or peripheral circuits, e.g., input-output (TO), still operate at higher voltages due to legacy and/or for backward compatibility. Level shifting is used for adjusting voltage differences from the core logic to IO interfaces.
In order to further reduce the power consumption of the core chip or core circuits, the power supply of the core chip or core circuits is decreased as much as possible without causing the core logic circuits (such as cache, register files, jam-latch sequential logics) to fail during operation (such as write or read mode) or standby situations. The minimum core-logic supply voltage is referred to as the Vccmin.
A high-voltage level shifter needs to be able to operate below or at close to the minimum operable power supply voltage of the core logic circuits. However, conventional high-voltage level shifters have problems operating at low Vccmin, e.g., fail level shifting or have very slow output slew rate.
Accordingly, new circuits and methods are desired to solve the above problems.